41 lines
1.8 KiB
NASM
41 lines
1.8 KiB
NASM
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; cache disable routine
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;
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public DisableCache
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code segment ; simple but effective for demonstration purposes
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;* DisableCache() *
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;* *
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;* This routine disables cache(s) on a 486 or Pentium processor *
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;* *
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;* NOTE: due to the protection schemes incorporated into the 486 and *
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;* Pentium processors, it will NOT work in virtual 8086 mode. *
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;* *
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;* written on Thursday, 2 November 1995 by Ed Beroset *
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;* and released to the public domain by the author *
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.486P
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CR0_CD equ 040000000h ; Cache Disable bit of CR0
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CR0_NW equ 020000000h ; Not Write-through bit of CR0
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DisableCache proc
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pushf ; save the flags
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push eax ; save eax
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cli ; disable interrupts while we do this
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mov eax,cr0 ; read CR0
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or eax,CR0_CD ; set CD but not NW bit of CR0
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mov cr0,eax ; cache is now disabled
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wbinvd ; flush and invalidate cache
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; the cache is effectively disabled at this point, but memory
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; consistency will be maintained. To completely disable cache,
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; the following two lines may used as well:
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or eax,CR0_NW ; now set the NW bit
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mov cr0,eax ; turn off the cache entirely
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pop eax ; restore eax
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popf ; restore the flags
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ret ; return to caller
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DisableCache endp
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code ends
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end
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